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| ? integrated circuits group lh 28 f 80 0 b vb - t t l 9 0 fla sh me mor y 8 m ( 1 m 8 / 512 k 16 ) (model no.: lh f 80 v 07 ) spec no.: el 11 4 06 7 issue date: a ugu st 27 , 19 99 p roduc t s pecific a tions
sharp lhfsovo7 @handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). *office electronics *instrumentation and measuring equipment *machine tools *audiovisual equipment *home appliance *communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliabilitv, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *control and safety devices for airplanes, trains, automobiles, and other transportation equipment *mainframe computers *traffic control systems l gas leak detectors and automatic cutoff devices *rescue and security equipment *other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. *aerospace equipment l communications equipment for trunk lines *control equipment for the nuclear power industry l medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. @please direct all queries regarding the products covered herein to a sales representative of the company. rev. 1.1 sliarp lhf80v07 1 contents page page 1 introduction.. ........................................................... .3 1. i features ........................................................................ 3 1.2 product overview.. ...................................................... .3 2 principles of operation.. ..................................... .7 2.1 data protection.. ........................................................... 8 5 design considerations ...................................... 20 5.1 three-line output control ....................................... 20 5.2 ry/by# and block erase and word/byte write polling.. .................................................................... 20 5.3 power supply decoupling ........................................ 20 5.4 v,, trace on printed circuit boards ........................ 20 3 bus operation ........................................................... .8 3.1 read.. ........................................................................... .8 3.2 output disable.. ........................................................... .8 3.3 standby ......................................................................... 8 3.4 deep power-down.. ..................................................... 8 3.5 read identifier codes operation.. ............................... .9 3.6 write.. ............................................. . ............................ .9 5.5 v,, . v,,, rp# transitions.. ..................................... 21 5.6 power-up/down protection.. .................................... 2 1 5.7 power dissipation.. ................................................... 21 4 command definitions.. ................ .: ......................... 9 4.1 read array command ................................................ 12 4.2 read identifier codes command ............................... 12 4.3 read status register command.. ............................... 12 4.4 clear status register command ................................. 12 4.5 block erase command.. ............................................. 12 4.6 word/byte write command.. ..................................... 13 4.7 block erase suspend command ................................ 13 4.8 word/byte write suspend command.. ...................... 14 4.9 considerations of suspend.. ....................................... 14 4.10 block locking.. ........................................................ 14 4.10.1 v,,=v,, for complete protection.. .................... 14 4.10.2 wp#=v,, for block locking.. ............................ 14 4.10.3 wp#=v,, for block unlocking.. ........................ 14 6 electrical specifications ............................... 22 6.1 absolute maximum ratings ..................................... 22 6.2 operating conditions ................................................ 22 6.2.1 capacitance.. ....................................................... 22 6.2.2 ac input/output test conditions ....................... 23 6.2.3 dc characteristics .............................................. 24 6.2.4 ac characteristics - read-only operations.. ..... 26 6.2.5 ac characteristics - write operations ............... 29 6.2.6 alternative ce#-controlled writes.. ................... 3 1 6.2.7 reset operations ................................................. 33 6.2.8 block erase and word/byte write performance 34 7 package and packing specifications ......... 35 rev. 1.1 sharip lhf80v07 2 lh28f8oobvb-ttl90 8m-bit (1mbit x 8 / 5 12kbit x 16) smart3 flash memory n smart3 technology - 2.7v-3.6v vcc - 2.7v-3.6v or 11.4v-12.6v vpp n user-configurable x8 or x 16 operation n high-performance access time - 90ns(2.7v-3.6v) n operating temperature - 0c to +7o?c n optimized array blocking architecture - two 4k-word boot blocks - six 4k-word parameter blocks - fifteen 32k-word main blocks - top boot location n extended cycling capability - 100,000 block erase cycles n enhanced automated suspend options - word/byte write suspend to read - block erase suspend to word/byte write - block erase suspend to read n enhanced data protection features - absolute protection with vpp=gnd - block erase and word/byte write lockout during power transitions - boot blocks protection with wp#=vil n automated word/byte write and block erase - command user interface - status register n low power management - deep power-down mode - automatic power savings mode decreases icc in static mode n sram-compatible write interface n chip size packaging - 48-ball csp n etoxtm* nonvolatile flash technology n cmos process (p-type silicon substrate) n not designed or rated as radiation hardened sharp?s LH28F800BVB-TTL90 flash memory with smart3 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F800BVB-TTL90 can operate at v,,=2.7v-3.6v and v,,=2.7v-3.6v its low voltage operation capability realize battery life and suits for cellular phone application. its boot. parameter and main-blocked architecture, flexible voltage and extended cycling provide for highly flexible :omponent suitable for portable terminals and personal computers. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either lirectly executed out of flash or downloaded to dram, the lh28f8oobvb-ttl90 offers two levels of protection: absolute lrotection with v,, at gnd, selective hardware boot block locking. these alternatives give designers ultimate control of their :ode security needs. ihe LH28F800BVB-TTL90 is manufactured on sharp?s 0.35um etoxtm* process technology. it come in chip-size lackage: the 48-ball csp ideal for board constrained applications. ?etox is a trademark of intel corporation rev. 1.1 sharp lhf8ovo7 3 1 introduction this datasheet contains lh28f800bvb-ti?l90 specifications. section 1 provides a flash memory overview. sections 2,3,4 and 5 describe the memory organization and functionality. section 6 covers electrical specifications. 1.1 features key enhancements of lh28f8oobvb-ttl90 smart3 flash memory are: *smart3 technology *enhanced suspend capabilities *boot block architecture please note following important differences: l vpplk has been lowered to 1.5v to support 2.7v-3.6v block erase and word/byte write operations. the v,, voltage transitions to gnd is recommended for designs that switch v,, off during read operation. *to take advantage of smart3 technology, allow v,, and v,, connection to 2.7v-3.6v. 1.2 product overview the LH28F800BVB-TTL90 is a high-performance 8m-bit smart3 flash memory organized as lm-byte of 8 bits or 512k-word of 16 bits. the lm-byte/512k-word of data is uranged in two 8k-byte/4k-word boot blocks, six sk- jytel4k-word parameter blocks and fifteen 64k-byte/32k- word main blocks which are individually erasable in- tystem. the memory map is shown in figure 3. smart3 technology provides a choice of v,, and v,, :ombinations, as shown in table 1, to meet system xrformance and power expectations. v,, at 2.7v-3.6v :liminates the need for a separate 12v converter, while v,,=12v maximizes block erase and word/byte write performance. in addition to flexible erase and program voltages. the dedicated v,, pin gives complete data protection when vpplvpplk. table 1. v,, and v,, voltage combinations offered by smart3 technoloav lzj i v,, voitage v,, voltage 2.7v-3.6v 1 2.7v-3.6v, 11.4v-12.6v 1 internal v,, and v,, detection circuitry automatically configures the device for optimized read and write operations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase and word/byte write operations. a block erase operation erases one of the device?s 32k- word blocks typically within 0.51s (2.7v-3.6v v,,, 11.4v-12.6v v,,), 4k-word blocks typically within 0.3 1s (2.7v-3.6v v,,, 11.4v-12.6v v,,) independent of other blocks. each block can be independently erased 100,000 times. block erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in word/byte increments of the device?s 32k-word blocks typically within 12.6~~ (2.7v-3.6v v,,, 11.4v-12.6v v,,), 4k- word blocks typically within 24.5~~ (2.7v-3.6v v,,, 11.4v-12.6v v,,). word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. rev. 1.1 sharp lhf8ovo7 4 the boot blocks can be locked for the wp# pin. block erase or word/byte write for boot block must not be carried out by wp# to low and rp# to v,,. the status register indicates when the wsm?s block erase or word/byte write operation is finished. the ry/by# output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using ry/by# minimizes both cpu overhead and system power consumption. when low, ry/by# indicates that the wsm is performing a block erase or word/byte write. ry/by#-high z indicates that the wsm is ready for a new command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in deep power-down mode. the access time is 90ns (tav temperature range (o?c to +70 43 v) over the commercial ) and v,, supply voltage range of 2.7v-3.6v. the automatic power savings (aps) feature substar&& reduces active current when the device is in static modf (addresses not switching). in aps mode, the typical i,, current is 3 ma at 2.7v v,,. when ce# and rp# pins are at v,-,, the i,, cm05 standby mode is enabled. when the rp# pin is at gnd deep power-down mode is enabled which minimize: power consumption and provides write protection during reset. a reset time (tphqv) is required from rp# switching high until outputs are valid. likewise, the device has i wake time (tphel ) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset ant the status register is cleared. the device is available in 48-ball csp (chip size package). pinout is shown in figure 2. rev. 1.1 sharp lhf8ovo7 5 duo-dqls r figure 1. block diagram 1 a 0 a? b 0 a3 c 0 al d 0 ao f 0 ce# 2 0 a5 0 % 0 a4 0 oe# 0 dq8 0 dqo 6 0 a8 0 nc 0 a9 0 dq6 0 dq5 0 ql? 7 0 all 0 aio 0 al? 0 qm 0 dq7 8 0 .%?i 0 ai? 0 al5 0 a16 4%ball csp pinout 8mm x 8mm top view figure 2. csp #-ball pinout rev. 1.1 sharp lhf8ovo7 6 r table 2. pin descriptions name and function symbol a-, ao-al8 type input address inputs: addresses are internally latched during a write cycle. a-1 : byte select address. not used in x16 mode. ao-alo : row address. selects 1 of 2048 word lines. all-*,, . . column address. selects 1 of 16 bit lines. < data input/outputs: dqo-dq-/:inputs data and commands during cui write cycles; outputs data during memory array, status register and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. dqs-dq, j:inputs data during cui write cycles in xl6 mode; outputs data during memory array read cycles in x 16 mode; not used for status register and identifier code read mode. data pins float to high-impedance when the chip is deselected, outputs are disabled. or in x8 mode (byte#=v,,j data is intemallv latched during a write cvcle. input/ output dqo-dq,, 1 chip enable: activates the device?s control logic. input buffers, decoders and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. with rp#=v,,, block erase or word/byte write can operate to all blocks without wp# state. block erase or word/byte write with vt, shari= lhf8ovo7 2.1 data protection depending on the application, the system designer may choose to make the v,, power supply switchable (available only when memory block erases or word/byte writes are required) or hardwired to vpphir. the device accommodates either design practice and encourages optimization of the processor-memory interface. when vppivpplk. memory contents cannot be altered. the cui, with two-step block erase or word/byte write command sequences, provides protection from unwanted operations even when high voltage is applied to v,,. all write functions are disabled when v,, is below the write lockout voltage v,,, or when rp# is at v,,. the device?s boot blocks locking capability for wp# provides additional protection from inadvertent code or data alteration by block erase and word/byte write operations. refer to table 6 for write protection alternatives. 3 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read [nformation can be read from any block, identifier codes jr status register independent of the v,, voltage. rp# can 5e at either v,, or v,,. the first task is to write the appropriate read mode :ommand (read array, read identifier codes or read status register) to the cui. upon initial device power-up x after exit from deep power-down mode. the device automatically resets to read array mode. six control pins dictate the data flow in and out of the component: ce#, 3e#, we#, rp#, wp# and byte#. ce# and oe# must be iriven active to obtain data at the outputs. ce# is the device selection control, and when active enables the ;elected memory device. oe# is the data output dqordqlj) control and when active drives the selected nemory data onto the i/o bus. we# must be at v,, and ip# must be at v,, or v,,. l figure 11 12 illustrates read , :ycle. 3.2 output disable with oe# at a logic-high level (v,,), the device outputs are disabled. output pins (dq,-dq,,) are placed in a high-impedance state. 3.3 standby ce# at a logic-high level (vrh) places the device in standby mode which substantially reduces device power consumption. dqo-dq,, outputs are placed in a high- impedance state independent of oe#. if deselected during block erase or word/byte write. the device continues functioning, and consuming active power until the operation completes. 3.4 deep power-down rp# at v, initiates the deep power-down mode. in read modes, rp#-low deselects the memory. places output drivers in a high-impedance state and turns off all internal circuits. rp# must be held low for a minimum of loons. time tphqv is required after return from power- down until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase or word/byte write modes? rp#-low will abort the operation. ry/by# remains low until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially erased or written. time tphwl is required after rp# goes to logic-high (v,,) before another command can be written. as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase or word/byte write modes. if a cpu reset occurs with no flash memory reset. proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. rev. 1.1 sharp lhf8ovo7 9 .5 read identifier codes operation 3.6 write he read identifier codes operation outputs the manufacturer code and device code (see figure 4). using le manufacturer and device codes, the system cpu can ltomatically match the device with its proper algorithms. writing commands to the cui enable reading of device data and identifier codes. they also control inspection ant clearing of the status register. when v,-=2.7v-3.6v ant vpt,=vpph1,2, the cui additionally controls block erasure and word/byte write. device code manufacturer code figure 4. device identifier code memory map the block erase command requires appropriate commanc data and an address within the block to be erased. the word/byte write command requires the command and address of the location to be written. the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. figures 13 and 14 illustrate we# and ce# controlled write operations. 4 command definitions when the v,, voltage iv,,,,. read operations from the status register, identifier codes, or blocks are enabled. placing vp,,,,* on v,, enables successful block erase and word/byte write operations. device operations are selected by writing specific commands into the cui. table 4 defines these commands. rev. 1.1 shari= lhf8ov07 read mode table 3.1. bus operations(byte#=vu.,)(l,z) notes rp# ce# oe# we# address v,, dq,,,5 ry/by#c3) 8 ?i, or vu, vi, vi, ?1, x x dout x output disable ?1, or ?hh vi, vi, ?1, x x high z x standby deep power-down read identifier codes write 10 ?1, or vnh ?1, x x x x high z x 4,lo vi, x x x x x high z high z 8 ?1, or viih vi, vi, ?1, see figure 4 x note 5 high z 6,7,8 viei or ?hh vi, vih vi, x x din x read mode table 3.2. bus operations(byte#=vil)(1,2) notes rp# ce# oe# we# address vw dq,, dq,-,, ry/by#(3)- 8 vih or vhh vi, vi, ?1, x x dour high z x output disable vih or vhh vil ?1, ?ih x x highz highz x standby deep power-down read identifier codes 10 ?1, or vhh ?1, x x x x high z high z x 4,lo vi, x x x x x high z high z high z 8.9 vih or vi, vi, ?1, see ?hh figure 4 x note 5 high z high z write fj 7 8 vihor > > vhh vil ?1, vil x x din x x notes: 1. refer to dc characteristics. when v,,5v,,,,, memory contents can be read, but not altered. 2. x can be vi, or vi, for control pins and addresses, and v,, or vpphijz for v,,. see dc characteristics for v,,, and v,,,,,, voltages. 3. ry/by# is v,, when the wsm is executing internal block erase or word/byte write algorithms, it is high z during when the wsm is not busy, in block erase suspend mode (with word/byte write inactive), word/byte write suspend mode or deep power-down mode. 4. rp# at gndk0.2v ensures the lowest deep power-down current. 5. see section 4.2 for read identifier code data. 6. command writes involving block erase or word/byte write are reliably executed when vpp=vpph1/2 and v,,=2.7v-3.6v. block erase or word/byte write with vm shari= lhf%ovo7 12 4.1 read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase or word/byte write. the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend or word/byte write suspend command. the read array command functions independently of the v,, voltage and rp# can be v,, or v,,. 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 4 retrieve the manufacturer and device codes (see table 5 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v,, voltage and rp# can be v,, or v,,. following the read identifier codes command, the following information can be read: table 5. identifier codes 4.3 read status register command the status register may be read to determine when a block :rase or word/byte write is complete and whether the operation completed successfully. it may be read at any ime by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid :ommand is written. the status register contents are atched on the falling edge of oe# or ce#, whichever occurs. oe# or ce# must toggle to v,, before further .eads to update the status register latch. the read status iegister command functions independently of the v,, joltage. rp# can be v,, or v,,. 4.4 clear status register command status register bits sr.5, sr.4. sr.3 or sr.l are set tc ?1?s by the wsm and can only be reset by the clear statu: register command. these bits indicate various failure conditions (see table 7). by allowing system software tc reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words/bytes ir sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently 01 the applied v,, voltage. rp# can be v,, or v,,. this command is not functional during block erase 01 word/byte write suspend modes. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written. followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffffh). block preconditioning, erase? and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written. the device automatically outputs status register data when read (see figure 5). the cpu can detect block erase completion by analyzing the output data of the ry/by# pin or status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected. the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to ?1?. also, reliable block erasure can only occur when vcc=2.7v-3.6v and vpp=vpph1,2. in the absence of this high voltage. block contents are protected against erasure. if block erase is attempted while v,,iv,,,,, sr.3 and sr.5 will be set to ?1?. successful block erase for boot blocks requires that the corresponding if set, that wp#=v,, or rp#=v,,. if block erase is attempted to boot block when the corresponding wp#=v,, or rp#=v,,, sr.l and sr.5 will be set to ?1?. block erase operations with vih shari= lim3ovo7 1.5 table 7. status register definition wsms 1 ess es 1 wbws 1 vpps 1 wbwss ( dps r 7 6 5 4 3 2 1 0 notes: sr.7 = write state machine status (wsms) check ry/by# or sr.7 to determine block erase or 1 = ready word/byte write completion. sr.6-0 are invalid while 0 = busy sr.7=?0?. sr.6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase if both sr.5 and sr.4 are ?1?s after a block erase attempt, an improper command sequence was entered. sr.4 = word/byte write status (wbws) 1 = error in word/byte write 0 = successful word/byte write sr.3 = v, status (vpps) 1 = v,, low detect, operation abort o=v,ok sr.2 = word/byte write suspend status (wbwss) sr.3 does not provide a continuous indication of v,, level. the wsm interrogates and indicates the v,, level only after block erase or word/byte write command sequences. sr.3 is not guaranteed to reports accurate feedback only when vyy~vyy,ll2~ 1 = word/byte write suspended 0 = word/byte write in progress/completed sr. 1 = device protect status (dps) 1 = wp# or rp# lock detected, operation abort 0 = unlock the wsm interrogates the wp# and rp# only after block erase or word/byte write command sequences. it informs the system, depending on the attempted operation, if the wp# is not v,,, rp# is not v,,. sr.0 = reserved for future enhancements (r) sr.0 is reserved for future use and should be masked out when polling the status register. rev. 1.1 sharp block address block address lhf8ovo7 16 erase loop check rf desired r?ll star?s check procedlxe bus operatm command commenls erase setup daw=?oh addr=wlthln block to be erased daa=doh addr=within block lo be erased read standby check sr.7 i=wsmready o=wsm busy repeat for subsequent block ems?res. full status check can be done after each block uasc or after a sequrnce of block crawrcs. command commentr standby check sr.3 l=vpp error dctcct standby chzck sr.1 i=devicz protect detect standby check sr.1.5 both i=command ssquencc error standby check sr.5 l=block erase error sr.5.sr.4.sr.3 and sr.1 us only cleared by tie clear status register command in cases where multiple blocks are erased beforc full status is checked. figure 5. automated block erase flowchart rev. 1.1 sharp lhl-?8uvu i i! start command coltl?x?ls write ioh or 10h. address wnrc wordap data and address 1 suspnd wwd/byte wrns loop dnladoh cx 10h setup word/byte write addr=locat,on to be wrmen data=data 10 bc wntwn word/byte wr,ts addr=loation to be wnttsn status rep,ster data check sr.7 i=wsm ready o=wsm busy full status check if deared word/byte wms complete fl-ll statcs check procedl?re read status reglstrr dala(see above) bus operation command . co?ull??ls standby check sr.? ,=vpp error dsr shari= writs bow lhf8ovo7 word/byte write completed word/byte writs resumed bus operation command comments data=boh ad&=x read standby check sr.7 i=wsm ready c=wsm busy standby check sr.? i=word/b~ze wrltc suspended o=word/b>zc writs completed rad array data=ffh ad&=x read word/b)~c write resume daa=doh addr=x figure 8. word/byte write suspend/resume flowchart rev. 1.1 siiarl= lhf80v07 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three-line control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the system?s read# control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should aiso toggle during system reset. 5.2 ry/by#, block erase and word/byte write polling rylby# is an open drain output that should be connected to v,, by a pull up resistor to provide a hardware method of detecting block erase and word/byte write completion. it transitions low after block erase or word/byte write commands and returns to high z when the wsm has finished executing the internal algorithm. ry/by# can be connected to an interrupt input of the system cpu or controller. it is active at all times. ry/by# is also high z when the device is in block erase suspend (with word/byte write inactive), word/byte write suspend jr deep power-down modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels. active current levels and transient peaks produced by falling and rising edges of ce# and oe#. transient currenl magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a o.lpf ceramic capacitor connected between its v,, and gnd and between its v,, and gnd. these high-frequency. low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7pf electrolytic capacitor should be placed at the array?s power supply connection between v,, and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 vpp trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v,, power supply trace. the v,, pin supplies the memory cell current for word/byte writing and block erasing. use similar trace widths and layout considerations given to the v,, power bus. adequate v,, supply traces and decoupling will decrease v,, voltage spikes and overshoots. rev. 1.1 sharp lhf8ovo7 21 5.5 vcc, vpp, rp# transitions block erase and word/byte write are not guaranteed if v,, falls outside of a valid vpphir range, v,, falls outside of a valid 2.7v-3.6v range. or rp##v,, or v,,. if v,, error is detected, status register bit sr.3 is set to ?1? along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v,, during block erase or word/byte write, ry/by# will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. device power-off or rp# transitions to v, clear the status register. the cui latches commands issued by system software and is not altered by v,, or ce# transitions or wsm actions. its state is read array mode upon power-up, after exit from deep power-down or after v,, transitions below vlko. after block erase or word/byte write, even after v,, transitions down to v,,,, the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. 5.6 power-up/down protection the device is designed to offer protection against lccidental block erasure or word/byte writing during power transitions. upon power-up, the device is indifferent as to which power supply (v,, or v,,) ?owers-up first. internal circuitry resets the cui to read u-ray mode at power-up. a system designer must guard against spurious writes for v,, voltages above v,,, when v,, is active. since botl- we# and ce# must be low for a command write, driving either to v,, will inhibit writes. the gui?s two-stey command sequence architecture provides added level o protection against data alteration. wp# provide additional protection from inadvertent cod< or data alteration. the device is disabled while rp#=v,, regardless of its control inputs state. 5.7 power dissipation when designing portable systems. designers must considel battery power consumption not only during device operation, but also for data retention during system idle time. flash memory?s nonvolatility increases usable battery life because data is retained when system power is removed. in addition, deep power-down mode ensures extremely low power consumption even when system power is applied. for example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering rp# to v, standby or sleep modes. if access is again needed, the devices can be read following the fphqv and tphwl wake-up cycles required after rp# is first raised to vih. see ac characteristics- read only and write operations and figures 11, 12> 13 and 14 for more information. rev. 1.1 sharp lhf8ovo7 22 6 electrical specifications 6.1 absolute maximum ratings* operating temperature during read, block erase and word/byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +7o?c(r) temperature under bias . . . . . . . . . . . . . . . . . . . . . . - 10c to +so?c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125?c voltage on any pin (except v,,, v,,, and rp#) . . . . . . . . . . . . -0.5v to +7.ov(*) v,, supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to +7.ov(*) v,, update voltage during block erase and word/byte write . . . . . . . . . -0.2v to +l 4.0v(2,3) *warning: stressing the device beyond the ?absolute maximan ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. notes: 1. operating temperature is for commercial temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0sv on input/output pins and -0.2v on v,, and v,, pins. during transitions, this level may undershoot to -2.ov for periods <20ns. maximum dc voltage on input/output pins and v,, is v,,+osv which, during transitions, may overshoot to vcc+2.0v for periods <20ns. 3. maximum dc voltage on v,, and rp# may overshoot to +14.ov for periods <20ns. rp# voltage _....................................... -0.5v to +14.0v(*y3) output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma(4) 4. output shorted for no more than one second. no more than one output shorted at a time. 6.2 operating conditions temperature symbol parameter min. max. unit test condition ta operating temperature 0 +70 ?c ambient temperature vcc vcc supply voltage (2.7v-3.6v) 2.7 3.6 v 5.2.1 capacitance( *) t,=+25?c, f=lmhz symbol parameter typ. max. unit condition cin input capacitance 7 10 pp v,,=o.ov ?out output capacitance 9 12 pp v,u,=o.ov vote: i. sampled, not 100% tested. rev. 1.1 sharp ac test inputs are driven at 2.7v for a logic ?1? and o.ov for a logic ?0.? input timing begins, and output timing ends, at 1.35v. input rise and fall times (107~ to 90%) ~10 ns. figure 9. transient input/output reference waveform for v,,=2.7v-3.6v ln914 cl includes jig capacitance figure 10. transient equivalent testing load circuit test confieuration caoacitance loading value test configuration c,(pf) vcc=2.7v-3.6v 30 lhf8ovo7 23 6.2.2 ac input/output test conditions rev. 1.1 shari= lhf80v07 24 6.2.3 dc characteristics dc characteristics v,,=27v-3.6v test sym. parameter notes typ. max. unit conditions il1 input load current 1 *os 11a vcc=vccmax. v,,=v,, or gnd il0 output leakage current 1 *os cul\ p=w- out=vcc or gnd kcs v,, standby current 1,336, cmos inputs 10 25 50 cla vcc=vccmax. ce#=rp#=v,,&2v 1,3,6 ttl inputs 0.2 2 ma vcc=vccmax. ce#=rp#=v,, ?ccd v,, deep power-down current 1,lo 5 10 lla rp#=gnd*0.2v iout(ry/13y#)=oma ?ccr v,, read current 1,596 cmos inputs 15 25 ma v,,=v,,max., ce#=gnd f=smhz, i,,,=oma tll inputs 30 ma vcc=vccmax., ce#=gnd f=smhz. iout=oma icc, v,, word/byte write current 137 5 17 ma v,,=2.7v-3.6v 5 12 ma v,,=11,4v-12.6v ?cc, v,, block erase current 1,7 4 17 ma v,,=2.7v-3.6v 4 12 nl4 v,,=11.4v-12.6v kcws v,, word/byte write or 12 ?cces block erase suspend current 1 6 ma ce#=v, ipps v, standby or read current 1 +2 &15 pa vpp~vcc ?ppr 10 200 pa vpp?vcc ?ppd vp, deep power-down current 1 0.1 5 i.ra rp#=gnd+0.2v ippw vp, word/byte write current 1,7 12 40 ma vpp=2.7v-3.6v 30 ma vp,=1 1.4v- 12.6v ?ppe v, block erase current 177 8 25 ma vpp=2.7v-3.6v 20 ma vpp=11.4v-12.6v ippws vp, word/byte write or 1 ?ppes block erase suspend current 10 200 cla vpp=vpphi i2 rev. 1.1 shari= lhf8ovo7 25 dc characteristics (continued) vo=2.7v-3.6v sym. parameter notes min. max. v,, low voltage input 7 -0.5 0.8 vih input high voltage 7 2.0 +?,c? vol output low voltage 337 0.4 ?ohi output high voltage 3.7 cl-rl) 2.4 ?oh2 output high voltage 3,7 0.85 (cmos) vcc 2% vpplk v, lockout voltage during normal 4,7 operations 1.5 ?pphl v, voltage during word/byte write or block erase operations 2.7 3.6 ?pph2 vp, voltage during word/byte write or block erase operations 11.4 12.6 2.0 vhh rp# unlock voltage 83 11.4 12.6 unit test conditions v v v yccz;=~in. ol v ycc~pccin~ oh- . v ;cflcdmin. oh . v vcc=vcc min. ioh?- loopa v v v v v unavailable wp# notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v,, voltage and t,=+25?c. 2. icc,, md ?cces are specified with the device de-selected. if read or wordlbyte written while in erase suspend mode, the device?s current draw is the sum of iccws or icces and iccr or icc,, respectively. 3. includes ry/by#. 4. block erases and word/byte writes are inhibited when vppivpplk, and not guaranteed in the range between vpplk(max.) and vpphl(min.), between vpphl(max.) and vpph2(min.) and above vpph2(max.). 5. automatic power savings (aps) reduces typical icc, to 3ma at 2.7v v,, in static operation. 6. cmos inputs are either vcc&0.2v or gndk0.2v. ttl inputs are either v,, or v,,. 7. sampled, not 100% tested. 8. boot block erases and word/byte writes are inhibited when the corresponding rp#=v,, and wp#=vl,. block erase and word/byte write operations are not guaranteed with vrh shari= llw8ovo7 27 vih iddresses vil standby oe#(g) :?i-- we#(w) hi f----- voh data(d/q) high z (dqo-dqd vol device address selection address stable data valid 4 --;~j high z i tavqv b ?cc tphqv vih i ~#(p) vil -----------7 figure 11. ac waveform for read operations rev. 1.1 sharp lhf8ovo7 28 ii vih .ddresses(a) vil standby oe#(g) y--- vih byte#(fj vtl _______---- voh ___________ data(d/q) high z (dqo-dq7) vol ___-_-_---- 4 device address selection data valid ____-______ address stable voh data(d/q) (dqs-dqls) vol high z data output high z figure 12. byte# timing waveform rev. i.1 sharp lhfsov07 29 6.2.5 ac characteristics - write operations(l) notes: 1. read timing characteristics during block erase and word/byte write operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 4 for valid a,, and d,, for block erase or word/byte write. 4. v,, should be held at v,,,t,z (and if necessary rp# should be held at v,,) until determination of block erase or word/byte write success (sr.1/3/4/5=0). 5. if byte# switch during reading cycle, exist the regulations separately. rev. 1.1 sharp lhf80v07 30 addresses(a) ce#(e) oe#(gl we#(w) data(d/ql byte#(f) ry/by#(r) wpw) rpnp) vppw bhhwh , vhh vih .- notes: 1. v,-c power-up and standby. 2. write block erase or word/byte write setup. 3. write block erase confirm or valid address and data 4. automated erase or program delay. 5. read status register data. 6. write read array command. figure 13. ac waveform for we#-controlled write operations rev. 1.1 sharp lhf8ovo7 6.2.6 alternative ce#-controlled writes(l) notes: 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup. hold, and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 4 for valid a,, and d,, for block erase or word/byte write. 4. v,, should be held at v,,,,,, ( and if necessary rp# should be held at v,,) until determination of block erase or word/byte write success (sr.1/3/4/5=0). 5. if bytb# switch during reading cycle, exist the regulations separately. rev. 1.1 shari= lhfsov07 32 addresses(a) ce#(e) oe#(g) wekw) data(d/q) byte#(f) ry/by#(r) wp#(s) rpmp) vih vil vih vil vih vih vih ,? no-l-es: 1. vcc power-up and standby. 2. write block erase or word/byte write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay 5. read status register data. 6. write read array command figure 14. ac waveform for ce#-controlled write operations rev. 1.1 sharp lhf8ovo7 reset operations ry/by#(r) vol vih rp#(p) vu (a)reset during read array mode high z ry/by#(r) vol vih rp#(p) vil (b)reset during block erase or word/byte write 2.w l vcc vu i - hvph - vih rp#(p) vil i (c)rp# rising timing figure 15. ac waveform for reset operation reset ac specifications v,,=2.7v-3.6v sym. parameter notes min. max. unit ?plph rp# pulse low time (if rp# is tied to v,,. this specification is not applicable) 100 ns tplrz rp# low to reset during block erase or word/byte write 12 22 p t2vph vcc 2.7v to rp# high 3 100 ns votes: 1. if rp# is asserted while a block erase or word/byte write operation is not executing, the reset will complete within loons. !. a reset time, tphqvz is required from the later of ry/by# going high z or rp# going high until outputs are valid. 3. when the device power-up, holding rp# low minimum ioons is required after v,, has been in predefined range and also has been in stable there. rev. 1.1 sharp lhf8ovo7 34 6.2.8 block erase and word/byte write performance(3) notes: 1. typical values measured at t,=+25?c and nominal voltages. subject to change based on device characterization. 2. excludes system-level overhead. 3. sampled but not 100% tested. 4. all values are in word mode (byte#=v,,). at byte mode (byte#=v,,), those values are double. rev. 1.1 sharp lhf80v07 35 7 package and packing specification 1. package outline specification refer to drawing no.aa2 0 3 4 2. markings 2 - 1. marking contents ( 1) product name : f800bvb- ttlso (2) company name : sharp ( 3 ) date code (example) y y indicates the product was manufactured in the wwth week of 19yy. - denotes the production ref.code (l-3) denotes the production week. (01,02,03, . . . * . 52,53) denotes the production year. (lower (4) the marking of ?japan? indicates the count 2-2. marking layout refer to drawing no.aa2 0 3 4 (this layout does not define the dimensions of marki two digits of the year.) ry of origin. ng character and marking position.) 3. packing specification (dry packing for surface mount packages) dry packing is used for the purpose of maintaining ic quality after mounting packages on the pcb (printed circuit board). if the surface mount type package absorbs a large amount of moisture, this moisture may suddenly vaporize into steam when the entire package is heated during the reflow soldering process. this causes expansion and results in separation between the resin and insert material, and sometimes cracking of the package. this dry packing is designed to prevent the above problem from occurring in surface mount packages. 3 - 1 . packing materials mater ial name material specificaiton purpose tray conductive plastic(loodevices/tray) fixing of device ___..________._.____.~~~~~~.~~~~..~~~~~-~~~~~-~~~~...-~~~~..---~~~~..-----~~~.~-.---~~~~~~~..-~~~~~~.~~~~~.~~~~~~.-~~~~~.------------------------ -------- upper cover tray conductive plast ic (it ray/case) fixing of device __.__.______...__.__~~..~~~~~---~~~~-~~~~..-~~~.-.--~--~~~~~~..~~~~~~~~...~~~~~~~~..---~~~~~~~~--~~~~~~~-~~~~~--~~~~~~~-~~~~~.~~~....----~.--------.--------- laminated aluminum bag aluminum polyethylene (lbag/case) drying of device _.__________.___________________________~~~~~~~~~~..~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.~.~~~~~~~~~~~~~~~~~~~~~~~~~~.~~~~~~...~~~~~...~~~~ des iccant silica gel drying of device _.__________________-~.~~~~~-~~~~~--~~~...-~~...----.-~-~~~~...~~~~~~~~.--~~~~~~~~..-~~~~~~~~~~--~~~~~~~-~~~~~-~~~~~~--~~~~..-~~~~.------...-------..-------- p p band polypropylene (5pcs/case) fixing of tray __________-_.____.---~.~~~-~~~~~~-~~~~~..--~~..-----.---~~~....~-~~~~~~~..---~~~~~~~~~----~~~~~~~-~~-~~ __.._____________---____________________---~~~..------ inner case card board (looodevices/case) packaging of device _________._______----~~~~~--~~~.--~~~~..---...-------~~~....---~~.....----~~~~....---~~~~~~..~~-~~~~~..-- ___----____----____.-~~~...----...-------.--------- label paper indicates part number,quantity and date of manufacture _.._______._.__._....~~~....~~~-.~~~~~~~~~~-~~~~...-~~~~--~-~~~~-~~-~~~~~~~~~-~--~~~~~~~-~-~.~~~~~---~~~~..~~~~~~~.~~~~~~--~~~~~-~~~~..-~~~~..-----...------- outer case card board outer packing of tray (devices shall be placed into a tray in the same direction.) sharp lhf80v07 36 3-2. outline dimension of tray refer to attached drawing 4. storage and opening of dry packing 4-l. store under conditions shown below befo (1) temperature range : 5-40c re opening the dry pack i (2) humidity : 80% rh or less 4-2. notes on opening the dry packing ng (1) before opening the dry packing, prepare a working table which is grounded against esd and use a grounding strap. (2) the tray has been treated to be conductive or anti-static. if the device is transferred to another tray, use a equivalent tray. 4-3. storage after opening the dry packing perform the following to prevent absorption of moisture after opening. (1) after opening the dry packing, store the ics in an environment with a temperature of 5--25c and a relative humidity of 60% or less. if doing reflow soldering once, mount ics within 4 days after the opening. if doing reflow soldering twice, do the first mounting within 4 days after the opening and do the second mounting within 4 days after the first mounting. (2) to re-store the ics for an extended period of time within 4 days after opening the dry packing, use a dry box or re-seal the ics in the dry packing with desiccant (whoes indicater is blue), and store in an environment with a temperature of 5-40c and a relative humidity of 80% or less, and mount ics within 2 weeks. (3) total period of storage after first opening and re-opening is within 4 days, and store the ics in the same environment as sect ion 4-3. (i). first opening+ xi +re-sealing+ y -?re-opening- xz -mount ing v ics in dry 5-25c 5-40c 5-25c packing 60%rh or less so%rh or less 60%rh or less 4 - 4. baking (drying) before mounting (1) baking is necessary (a) if the humidity indicator in the desiccant becomes pink (b) if the procedure in section 4-3 could not be performed (2) recommended baking conditions if the above conditions (a) and (b) are applicable, bake it before mounting, the recommended conditions are 1-3 hours at 120 ~~??c. heat resistance tray is used for shipping tray. (3) storage after baking after baking ics, store the ics in the same environment as sect ion 4-3. (1). , sharp lhf80v07 37 5. surface mount conditions please perform the following conditions when mounting ics not to deteriorate ic quality. 5-l. ,soldering conditions mounting method temperature and duration measurement point reflow soldering peak temperature of 240c or less, ic package surface duration of less than 15 seconds above 230c. 200c or over ,durat ion of 30-50 seconds. preheat temperature of 125~150c duration of less than 180 seconds. temperature increase rate of l--4?c/second. 5- 2. conditions for removal of residual flux (1) ultrasonic washing power : 25 watts/liter or less (2) washing time : total 1 minute maximum ( 3 > solvent temperature : 15-40c j sharf? lhf80v07 i ,i ndex top view------ v f8oobvb- ttlso japan 0. 4 t?tf. a p_ -- bottom view ---_ i \ -:? \ \ i 1 j( 0 i i i i \ i i\ \ / \ \ \ a-l \ / ?. .? ? 0 --___-y . 01 i i 1. 2 typ. t - $ 60. 30 @ s ab i cbo.45 20.03 ,z- @@0.15@ scd %lq tb% name ; fbga048-p-0808 note %im i drawing no. i aa2034 unit ! mm sharp lhf80v07 -r - f h : 1 c a a %vf~ fiiwi jame 1 lcsp80-0808tct-rh note p.3 !7.9 25.0~0.3*4=100.0~0.3 17.4 5.8 r i 35.8 2:: w i+.&{z ; drawing no. / cv812 unit 1 mm sharf= lhe3ovo7 40 flash memory lhfsov(b)xx family data protection (tsop package, csp package) noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. such noises, when induced onto we# signal or power supply, may be interpreted as false commands, causing undesired memory updating. to protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) protecting data in specific block by setting a wp# to low, only the boot block can be protected against overwriting. parameter and main blocks cannot be locked. system program, etc., can be locked by storing them in the boot block. when a high voltage is applied to rp#, overwrite operation is enabled for all blocks. for further information on controlling of wp# and rp#, refer to the specification. (see chapter 4.10) 2) data protection through vpp when the level of vpp is lower than vpplk (lockout voltage), write operation on the flashmemory is disabled. all blocks are lockedandthedata intheblocksarecompletely write protected. for the lockout voltage, refer to the specification. (see chapter 4.10 and 6.2.3. > 3) data protection through rp# when the rp# is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting all blocks. for the detai 1s of rp# control, refer to the specification. (see chapter 5.6 and 6.2.7. > 4) noise rejection of we# consider noise rejection of we# in order to prevent false write command input. rev 1.1 |
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